Quantum Compilation

From quantum circuits
to hardware execution

A circuit describes the computation. Compilation determines how it can run on a particular machine, and what that implementation will cost.

Explore the problemOur approach with Weylattice

01 / The compilation problem

Preserve the computation.
Choose its implementation.

A quantum algorithm is expressed through operations on logical qubits. A processor offers a specific instruction set, a pattern of allowed interactions, and constraints on timing and resources. Compilation connects these two descriptions.

The task is to construct an executable implementation that preserves the intended computation while reducing a chosen cost. Many implementations can be equivalent, yet differ substantially in the work required to execute them.

Input

The computation

The circuit, its dependencies and the behaviour that must be preserved.

Constraints

The target architecture

Supported operations, connectivity, timing and available device information.

Objective

The implementation cost

Gate count, depth, duration or an error model, under a practical compilation budget.

A constrained optimisation problem

C⋆∈argmin⁡C∈C(H)  J(C;H,K)subject toC≃εC0.C^\star \in \underset{C\in\mathcal C(H)}{\operatorname{argmin}}\;J(C;H,K)\qquad\text{subject to}\qquad C\simeq_{\varepsilon} C_0.
C0C_0
The input computation.
C(H)\mathcal C(H)
Implementations permitted by target HH.
JJ
The chosen cost, using device information KK where relevant.
ε\varepsilon
An explicit tolerance when approximate synthesis is allowed.

The expression defines the optimisation goal; practical methods need not find a global optimum. For unitary circuits, equivalence accounts for global phase and tracked qubit mappings. Measurement and classical control require the corresponding notion of program equivalence.

02 / Importance and pain points

Small overheads.
Large consequences.

As workloads grow, repeated compilation decisions accumulate into substantial execution costs. IBM’s roadmap illustrates the scale being targeted: circuits containing hundreds of millions to a billion gates on error-corrected systems.

These are planned circuit capacities. They make efficient implementation and scalable compilation increasingly consequential research problems.

IBM Quantum Starling / Target: 2029

100million gates

On 200 logical qubits

IBM Quantum Blue Jay / Target: 2033+

1billion gates

On up to 2,000 logical qubits

IBM roadmap and fault-tolerance announcement. Roadmap targets are subject to change. Counts describe circuit size, not gates per second.

1% of a billion gates is 10 million operations.

This is an arithmetic illustration, not a measured compiler result. The execution benefit depends on which operations are removed and how they affect the critical path.

01

Routing adds physical work

An interaction between distant qubits can require movement of quantum information. Added SWAPs must themselves be implemented using the target’s native operations, increasing the resources needed for the computation.

02

Decisions affect what comes next

A placement determines the routing problem. A route changes the qubit mapping and later optimisation opportunities. A choice that helps the next gate can make subsequent interactions more expensive.

03

Performance objectives compete

Fewer gates need not mean a shorter execution. Operation durations, parallelism and error characteristics also matter. The objective must specify which costs are important for the workload and target.

04

Compilation must also scale

Searching more candidates consumes classical time and memory. A practical compiler must balance the quality of its output against the cost of finding it, including any model inference used in its decisions.

Fault tolerance changes the cost model.

Error-corrected machines still need compilation. Logical instructions, communication between modules and resources such as magic-state preparation introduce their own constraints. The broader compilation problem persists, although the appropriate actions and objectives differ from physical SWAP routing on today’s devices.

03 / Current approaches

Structure, synthesis
and heuristic search.

Established compilers combine algebraic rewrites, circuit synthesis and search. Exact or numerical methods can optimise bounded subproblems; heuristics help navigate larger placement and routing spaces. Each method balances solution quality with computational effort.

Qiskit coordinates analysis and transformation passes through a configurable pipeline. Its standard stages organise the work, while the algorithms inside those stages make the individual decisions.

Qiskit’s compilation framework
  1. 01init

    Initialisation

    Prepare the circuit and decompose higher-order operations as required.

  2. 02layout

    Layout

    Choose where the logical qubits are placed on the device.

  3. 03routing

    Routing

    Introduce operations that make interactions compatible with connectivity.

  4. 04translation

    Translation

    Express the circuit using the target instruction set.

  5. 05optimization

    Optimisation

    Simplify and resynthesise parts of the resulting circuit.

  6. 06scheduling

    Scheduling

    Assign timing and account for idle periods when requested.

Stages can contain iterations and conditional passes. Their order matters: a decomposition can expose cancellations, a layout changes the routing task, and routing can create new optimisation opportunities.

Inside the routing stage

How SABRE chooses a SWAP

SABRE tracks dependency-ready gates and the current qubit mapping. It executes available interactions; when routing is needed, it scores nearby candidate SWAPs using hardware distances. Look-ahead includes upcoming gates, while a decay term can discourage repeatedly using the same qubits.

The selected SWAP changes the mapping, and the process continues. Qiskit’s implementation incorporates LightSABRE improvements and supports multiple seeded trials. These are useful baselines for evaluating both routing quality and compilation speed.

SABRE paperLightSABRE

A single routing decision

Pending interaction: q₀ and q₂

Four physical qubits connected in a lineInitially, logical qubits q0, q1, q2 and q3 occupy physical qubits p0, p1, p2 and p3. Qubits q0 and q2 are not adjacent. Either swapping p0 with p1, or swapping p1 with p2, makes this interaction adjacent. The two actions leave different mappings for later gates.q0p0q1p1q2p2q3p3
Candidate ASWAP(p₀, p₁)
Candidate BSWAP(p₁, p₂)
Both candidates make the pending pair adjacent. They leave different mappings, so upcoming interactions matter. Illustrative bidirectional topology; native gate translation is omitted.

The research question is how well a decision rule captures the downstream consequences of each action, within the time available to make that decision.

04 / Weylattice

Learning the next
compilation decision.

Weylattice is QuantGates’ quantum compilation engine. Our research direction is to use learned circuit and hardware representations to guide elementary compilation actions, beginning with routing.

We are investigating Transformer-based representations of circuit dependencies, target connectivity and the current mapping, coupled to a learned scorer for legal SWAPs. The aim is to make the relationships between current and upcoming interactions inform the next action.

Proposed routing architecture

01

Represent the state

Encode dependencies, ready gates, future interactions, hardware connectivity and the current logical-to-physical mapping.

02

Score legal actions

Use a learned model to estimate the downstream cost of candidate SWAPs under the selected compilation objective.

03

Apply and continue

The deterministic compiler applies the selected legal operation, updates the mapping and emits any newly available gates before the next decision.

at⋆∈argmin⁡a∈Alegal(st)  J^θ(st,a)a_t^\star \in \underset{a\in\mathcal A_{\mathrm{legal}}(s_t)}{\operatorname{argmin}}\;\widehat J_\theta(s_t,a)

Here, sts_t is the current routing state, Alegal(st)\mathcal A_{\mathrm{legal}}(s_t) is the set of eligible legal actions and J^θ\widehat J_\theta is a learned cost estimate. This is a proposed decision rule. Correctness rests on legal transformations and explicit mapping updates, independently of the model’s ranking quality.

Evaluate the complete route.

A locally attractive move is useful only if its consequences improve the complete implementation. Evaluation must therefore compare complete routing trajectories under matched targets, objectives and compilation budgets.

A central research question is whether learned decisions improve downstream cost enough to justify inference time. Generalisation to unseen circuits and bounded memory use are part of that question.

Implementation quality
Native two-qubit operations, routing overhead, depth and scheduled duration where available.
Classical cost
End-to-end compilation time and peak memory, including representation and inference.
Validity and robustness
Preserved semantics, target compliance, different circuit families and repeated seeded trials.
Execution evidence
Distinguish estimated error objectives from results measured on quantum hardware.

Explore the product

Weylattice in Spinorio Lab

Prepare, inspect and compare circuits for a selected target. Explore the current product and its compiler guide.

Explore WeylatticeRead the compiler guide